Key Research Areas

Circuits and System Design, Spectrum Sensing for Cognitive Radio Technology, Channel Decoders for Next-Generation Communication Systems


On October 2014, I defended my Doctoral Thesis under the supervision of Prof. Roy P. Paily in the Department of Electronics & Electrical Engineering, Indian Institute of Technology Guwahati (IIT-G). Thereafter, I joined as Assistant Professor in the Center for VLSI and Embedded System Technologies (CVEST), International Institute of Information Technology Hyderabad (IIIT-H). I received Early Career Research Award from the Science and Engineering Research Board (SERB), Department of Science & Technology (DST), Government of India, in the year 2015. Currently, I hold the position of Associate Professor in the School of Computing and Electrical Engineering (SCEE), Indian Institute of Technology (IIT) Mandi. In the year 2018, I was selected as the Visiting Assistant Professor at the Blekinge Institute of Technology, Karlskrona, Sweden, under the European Erasmus+ International Credit Mobility Programme. At IIT-Mandi, I am heading a very enthusiastic research group that is working in the field of designing efficient algorithms & digital VLSI architectures, its transformation into ASIC chip or FPGA prototype for the real world applications of signal processing, wireless communication, deep neural network, forward-error-correction channel decoders, cognitive radio, and cooperative spectrum sensing. We have published our various research works in more than 22 reputed journals and 32 tier-1 conferences. In the year 2020, I have been elevated to the Senior Member of Institute of Electrical and Electronics Engineers (IEEE), USA.

Recent Publications

1. A. Verma and R. Shrestha, "Low Computational-Complexity SOMS-Algorithm and High-Throughput Decoder Architecture for QC-LDPC Codes," IEEE Transactions on Vehicular Technology, pp. 1-14, 2022, doi: 10.1109/TVT.2022.3203802.
2. M. N. Islam, R. Shrestha, and S. R. Chowdhury, "An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-11, 2022, doi: 10.1109/TVLSI.2022.3210963.
3. R. B. Chaurasiya and R. Shrestha, "Design and ASIC-Implementation of Hardware-Efficient Cooperative Spectrum-Sensor for Data Fusion-Based Cognitive Radio Network," IEEE Transactions on Consumer Electronics, vol. 68, no. 3, pp. 221-235, 2022, doi: 10.1109/TCE.2022.3167471.
4. R. B. Chaurasiya and R. Shrestha, "Fast Sensing-Time and Hardware-Efficient Eigenvalue-Based Blind Spectrum Sensors for Cognitive Radio Network," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 4, pp. 1296-1308, 2020, doi: 10.1109/TCSI.2019.2941762.
5. R. B. Chaurasiya and R. Shrestha, "Hardware-Efficient and Fast Sensing-Time Maximum-Minimum-Eigenvalue-Based Spectrum Sensor for Cognitive Radio Network," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 11, pp. 4448-4461, 2019, doi: 10.1109/TCSI.2019.2921831.

Course Taught

1. EE-524: Digital MOS IC Design
2. EE-519P: CMOS Digital IC Design Practicum
3. EE-210P: Digital System Design Practicum
4. EE-529: Embedded Systems
5. IC-160P: Applied Electronics Laboratory
6. EE-512: Analog CMOS-IC Design
7. EE-523: Digital VLSI Architectures Design.